Pilot corpus: NIH-funded biomedical datasets. Any DOI can be scored on demand — network effects sharpen as coverage grows.

Mixed-Signal Charge-Domain Acceleration of Deep Neural Networks through Interleaved Bit-Partitioned Arithmetic

arXiv (Cornell University)(2020)10.1145/3410463.3414634Source: DataRank Database

Mixed-Signal Charge-Domain Acceleration of Deep Neural Networks through Interleaved Bit-Partitioned Arithmetic is a research paper published in arXiv (Cornell University) (2020). On theSindex it has a DataRank of 0. It has been cited 4 times.

N/A

0DataRank · unranked

Scored on demand from live citation data

Open Access4 citations

Free full text

Cite:

DataRank reads this dataset's downstream impact straight off the citation graph — no black box, no proprietary weighting. How is this computed?

›Methodology & internals

datarank_citation_only_1hop_v6· scope data_onlyMethodology

Pipeline:MetadataData-paper checkEnrichmentCitation networkScoring

Enrichment:Funding (3 grants)OA: goldTopics (7)IDs (PubMed)

FAIR Checklist

Context only (not used in score)

Findable (1/2)

Has DOI

Accessible (1/2)

Open Access

Interoperable (0/2)

Reusable (0/3)

FAIR checklist signals are shown for context only and do not affect DataRank scoring.

Run a calibrated FAIR evaluation for this paper →

We only score data papers we can read in full — never from an abstract alone.

Authors (8)

Hardik Sharma ORCID,Sean Kinzer ORCID,Amir Yazdanbakhsh ORCID,Jongse Park,Nam Sung Kim ORCID

Live enrichment

PubMed:19965766

National Institutes of Health

Grant: 5R01EB028350-02

A framework for developing translatable intelligent neural interface systems for precision neuromodulation therapies

National Science Foundation

Grant: 1703812

CSR: Medium: Collaborative Research: Scale-Out Near-Data Acceleration of Machine Learning

National Science Foundation

Grant: 1553192

EAGER: Language and Architecture Design for Approximation at Different Granularities

goldLicense: cc-by

https://dl.acm.org/doi/pdf/10.1145/3410463.3414634

repositoryhttps://arxiv.org/pdf/1906.11915

repositoryhttps://doi.org/10.48550/arxiv.1906.11915

https://doi.org/10.1145/3410463.3414634

https://dx.doi.org/10.48550/arxiv.1906.11915

Fields of Study

0103 physical sciences0202 electrical engineering, electronic engineering, information engineering02 engineering and technology01 natural sciences

Keywords

FOS: Computer and information sciencesHardware Architecture (cs.AR)Computer Science - Hardware Architecture

Related Papers (8)

Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array

Proceedings of the International Symposium on Low Power Electronics and Design(2018)

OpenAlex related

10.1145/3218603.3218605

Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead

(2020)

OpenAlex related

10.1109/dac18072.2020.9218657

aCortex: An Energy-Efficient Multipurpose Mixed-Signal Inference Accelerator

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits(2020)

OpenAlex related

10.1109/jxcdc.2020.2999581

An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration

(2019)

OpenAlex related

10.1109/iscas.2019.8702357

An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing

(2019)

OpenAlex related

10.1109/nanoarch47378.2019.181284

Compute-in-Memory Primitives for Energy-Efficient Machine Learning

Purdue e-Pubs (Purdue University System)(2021)

OpenAlex related

10.25394/pgs.15048825.v1

Special Topic on Exploratory Devices and Circuits for Compute-in-Memory

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits(2020)

OpenAlex related

10.1109/jxcdc.2020.3001859

Digital Neuron: A Hardware Inference Accelerator for Convolutional Deep Neural Networks

arXiv (Cornell University)(2018)

OpenAlex related

10.48550/arxiv.1812.07517